Scheme unwinding testimony induction meters on the chip To LP and Cle
Probably many are familiar with this option reduce the indications of counting devices as a normal unwinding. This system works in cases where you have in stock induction meter. In the case of counters, electronic or electro-mechanical, returning to Unscrew fail, but to reduce consumption almost to the losses in the wires is possible and very easy. In the diagram, all the settings worked out under AC 220V, 1KW load (iron). If you want to use with load more than 1 KW, you will need to slightly alter the data in the diagram. Works just like a clock! Plugged the device and the system stops counting killowat. You do not damage any wiring or anything of such a serious not doing everything for you makes electronics. Do not even need to do additional grounding. The system works using a simple physical processes. All electronic meters have a low sensitivity to high frequency currents. Energy consumption can be reduced if to consume the energy of high frequency pulses. In counters, there is also the relay orientation (but not all of it is), if you served in the network voltage from the generator, then considers the counter in the opposite direction. In our case this will not happen, we will either rewind or stop the counter.
There is a printed circuit Board and circuit Board. What we see on the Board schematic There is an integrator in a bridge circuit R1-R4, the pulses are removed from the capacitor C1. Pulses of the chain, the Zener diodes D1, D2 and resistors R5, R6. Block, the elements DD1.1, DD2.1, DD2.2 is a logical node. Module DD2.3, DD2.4 — the processor clock. Assembly T1, T2 is a transistor amplifier. The Assembly of the C2, T3, Br1-output stage.
what is each block
Integrator selects a supply voltage of clock signals for stable operation of the logical node. Something similar to there is a level or not on the TTL input at inputs 1 and 2 of the element DD1.1. As the positive half wave is coming from the supply network, the signal is, how negative it is not. The maximum signal level at the 2nd entrance DD1.1 when the integrator is positive half wave. In General everything is clear is rectangular snake with the network synchronization. There is a phase offset of PI/2. Network signal hits the divider R1, R3 (5V), this level is achieved through R5 and the Zener diode D2. Next, the signal goes to the optocoupler OC1 which manages the logical node. This way is the formation of signal integration, it is removed from the capacitor C1. The units are similar for the scheme. All you need to regulate the opening and closing of the transistor T3 (closed helmets amplifier circuit). The two signals are compared by the algorithm. From 4 feet DD2.2 are taken directly to control T3 At some stage, the modulating signal is the great, short PTO. Thus is being built the high-frequency power. The transistor T3 has a short period to fully open, and then just as quickly closed. If you have the time great on transients, it will burn very quickly overheat. Such a device that will allow you to feed any load from 36V when the load current up to 2A. Difficulties with repetition of this unit should arise, great concept all shown and painted.
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